Principal Analog Design Engineer

Overview

Principal Analog Design Engineer

Pavia, Italy

€85,000 to €110,000 + Bonus + SIGNING BONUS + Paid Relocation

This role is a key position within our Optical PHY (CE-OPHY) team, which is part of our Central Engineering division. Our team is at the forefront of designing high-speed and optical transceivers for modern communication infrastructure. This technology is critical for addressing the explosive demand for bandwidth in mega data centers that power social media, video-on-demand, gaming, and other real-time data streams. We are dedicated to developing innovative, first-to-market chips and subsystem solutions that push the boundaries of data rates and power efficiency.

Responsibilities

• Design & Architecture: analyze and interpret block specifications, take ownership of transistor-level design, and select the most appropriate topologies. Design entire analog macros or IPs from initial concept to final mass production.
• Verification & Validation: model and validate circuit blocks; supervise layout activities, provide clear guidelines, and conduct rigorous post-layout verifications to ensure design integrity.
• Collaboration & Leadership: work closely with other engineering teams to enhance existing solutions; participate in cross-functional meetings; train and mentor junior designers to build the team's expertise.
• Project Management: manage pre-silicon tasks (simulation and modeling) and post-silicon tasks (lab characterization, debugging, correlating measurements to simulations) through to high-volume production.

Candidate Profile

• Education & Experience: A Master's degree or Ph.D. in Electrical Engineering or a related field is required, with 12-15 years of professional experience.
• Technical Skills: proven experience designing ICs from architecture definition through lab characterization and volume production; strong background in analog design (preferably multi-GHz); experience supervising custom analog layout, using standard EDA CAD tools, and debugging designs to correlate simulations with measurements.
• Preferred Qualifications: Experience with multi-Gbps electrical SerDes or electro-optical transceivers; knowledge of advanced CMOS nodes, including FinFET, is advantageous.
• Personal Skills: strong communication, presentation, and documentation skills; proficiency in Italian and English (minimum B2) due to an international team and location.
• Work Model: On-site, full-time position located in Pavia, Italy.

#J-18808-Ljbffr