Principal Functional Verification Engineer

As a Functional Verification Principal Engineer , you will interface with architecture, design, physical implementation and software teams to ensure systems perform at the highest level. Your work will include high‑level modelling, UVM, HW/SW co‑debug, and simulation acceleration support.

Key Responsibilities

• Reading and analysing system requirements and architecture requirement documents.
• Developing detailed test and coverage plans based on architecture and micro‑architecture.
• Developing verification methodology, ensuring scalability and portability across environments.
• Developing verification environment in SystemVerilog/UVM/SystemC/C++, including components such as stimulus, checkers, assertions, trackers, and coverage.
• Executing verification plans, including design bring‑up, DV environment bring‑up, regressions, and debugging of test failures.
• Using standard tools and flows of the verification process (simulators, coverage analyzers, Unix, continuous integration, bug tracking, etc.).
• Creating and executing test cases to verify functionality, performance, and robustness in embedded C and SV.
• Identifying, isolating, and debugging issues found during verification, leveraging simulation and debugging tools to root‑cause failures and drive resolution with design and architecture teams.
• Working closely with cross‑functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure quality and completeness of verification activities.
• Organizing work and deliverables between skills, internal and external teams.
• Mentoring and training the next generation of verification engineers.
• Coordinating functional verification teams.

Required Skills and Experience

• Master’s degree in a relevant field.
• Minimum 15 years of experience in verification of complex SoC or IP.
• Experience in SystemVerilog/UVM.
• Experience in SystemC/C++.
• Experience in constrained‑random, functional coverage development, design debug.
• Experience in formal verification, UPF.
• Experience in HW‑SW co‑verification and simulation.
• Some previous experience in firmware‑based verification is a good to have.
• Knowledge of scripting languages like Bash, Perl, Python.
• Use of verification management tools.
• Strong debugging and problem‑solving skills, with the ability to effectively analyze and resolve complex verification issues.
• Good level of English, both written and spoken, is mandatory.

Preferred Qualifications

• Experience in firmware‑based verification.
• Knowledge of metrics‑driven verification.
• Insights of NOC and other IPs or standard peripherals like PCIe, DDR, HBM.

Soft Skills

• Team player, able to work with multiple cultures both on site and remotely.
• Autonomous and flexible.
• Strong leadership and communication abilities.

What We Offer

• Join an innovative team and experience company growth.
• Invest in employees and provide opportunities for career development.
• Hybrid work environment.
• Flexible schedule.
• Competitive remuneration that values your experience.
• Base location in Rome.

We believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.